NexGen Nx586 multiplier and FSB

[feipoa]

Does anyone know what multiplier a NexGen Nx586 uses? Alternately, what FSB is used? From what I gather, the

P110 runs at 102 MHz
P100 runs at 93 MHz
P90 runs at 84 MHz

Is there some common FSB, e.g. between 33-75 MHz, that the accompanying motherboards run with?

Often, the PCI bus is set to Async 32 MHz, however there is a jumper option to set the PCI bus to run Sync, and I assume that is Sync with the FSB. Any idea what the FSB might be?

[H3nrik V!]

If we expect multiplier to be in steps of 0,5 (which is highly probable from a technical point of view) I can't see what common fsb the three could have ..

[frag_]

Afaik multiplier is fixed as 2x.
Motherboard clockgen chip handles all the strange frequencies:
http://www.cpu-world.com/forum/viewtopic.php?t=24340

[feipoa]

Thank you for this information. The Clock generator chip on my PF110 is

ICS9159M
9533-07

I assume this corresponds to the ICS9159M-07 datasheet found here: https://pdf1.alldatasheet.com/datasheet-pdf/view/65556/ICST/ICS9159-07.html

According to this datasheet, the output frequency options are:

64.98
60.03
55.50
51
46.53
42
37.48
35
10

If the PF110 runs at 102 MHz and the multiplier if fixed at 2x, this implies that the front-side bus is running at 51 MHz. This is one of the outputs of the clock generator chip.

So it seems to me that the P100 (93 MHz) has an FSB of 46.53, and the P90 (84 MHz) an FSB of 42 MHz.

When I tried to set the motherboard jumpers for the PCI bus to run Sync, all I get is a black screen. At 51 MHz, I can understand this outcome. However, what I do not understand is why I measure 34 MHz on the PCI slot when set to Sync. Why does the scope not read 51 MHz? When I set the jumpers to Async, the scope reads 32 MHz as expected. Attached are some oscilloscope screen captures.

[cuttingedgecs]

I don't know enough about these, but your answer may lie in the fact that 3 x 34 = 102. I would try running the chip at a lower speed and see if you get a corresponding drop in PCI speed. It may well be that the board knows better than to run PCI at 51MHz, so 34MHz is it's way of running semi-syncronous

[xsecret]

Nx586 works internally with a Dual Phase clocking scheme. 3 modes are available to provide the clocks :

1. Using the internal PLL to generate the 2 phases, synchronized with an input clock at half the frequency (33 MHz for Nx586-P66). That's the most common mode in retail boards.

2. Using the internal PLL to generate the 2 phases, synchronized with an input clock at the required frequency (66 MHz for Nx586-P66). That's for the board with the Nx587 Socket.

3. Provide directly the two internal phases to the Nx586, bypassing the internal PLL. That's for the development board with Nx586-P60/66

The P-Rating is used for 75+ Nx586, with real frequencies being:

P60 : 30 MHz (x2)
P66 : 33.3 MHz (x2)
P75 : 35 MHz (x2)
P80 : 37.5 MHz (x2)
P90 : 42 MHz (x2)
P100 : 47.5 MHz (x2)
P110 : 51 MHz (x2)
P120 : 55.5 MHz (x2)
P133 : 60 MHz (x2)

[feipoa]

xsecret, thanks for the additional information. I'm still a little confused about what frequency the PCI bus should be receiving in Sync mode. For the P110, is it 51 MHz? And what is the freq. that the memory is run it, also 51 MHz?

[H3nrik V!]

[feipoa]

I used a digital storage oscilloscope (DSO) with a bandwidth of 100 MHz and sample rate of 1 GSa/s.

[H3nrik V!]

[mtx500]

An Nx586 topic popping up while I am on vacation with a weak internet connection - ahh!

[alexino2]

Hello,

It's very hard to find some informations on how a cpu behave with a FSB.

For example you have a 400Mhz Cpu with 100Mhz FSB, what I don't understand is in which case it's useless to have so many cpu speed (because limited by FSB/Ram) ? And in reverse, how the processor works internaly, when everything else is 4x times slower and can't follow the cpu ?

[feipoa]

The NexGen databook mentions that the L2 cache can run either Async or Sync. The CPU runs at twice the NexBus (NxCLK, which I assume is the 51 MHz front-side bus). The CPU's L1 cache runs at twice the frequency of the CPU, or four times more than NexBus. The L2 cache runs at NexBus.

I couldn't locate any information in the databook about the PCI frequency, only a FAQ in the PCI troubleshooting guide mentions the PCI bus is run at 32 MHz async. Perhaps it is not correct to assume that running the PCI bus Sync really mean it runs at NexBus. It could mean that a Sync PCI bus is just run through another PLL which locks in the PCI phase, e.g. to the rising edge of NexBus,but still runs at 34 MHz Sync. Whatever PLL is used for Sync is likely set to be a 2/3 multiplier, that is, 51 * 2/3 = 34 MHz. 2/3 is a common multiplier used on this generation of motherboard, e.g. a Biostar MB-8433UUD uses a 2/3 multiplier to multiply a 50 MHz FSB by 2/3 so that the PCI bus is run in spec at 33.33 MHz.

This still begs the question of why the motherboard shows a blank screen when the PCI bus is set to Sync. What extra step am I missing?

[cvandijk]

Bitsavers also has the databooks, but searchable:

http://www.bitsavers.org/pdf/nexGen/

DxDOC-DB001-03_W_Nx586_Processor_Databook_Dec94.pdf

DxDOC-DB001-01-W_Nx586_Processor_and_Nx587_Floating_Point_Coprocessor_Databook_Apr94.pdf

NxDOC_DB002-01-W_NxVL_System_Controller_Databook_Apr94.pdf

[feipoa]

Does anyone know if there were any NexGen-specific computer cases?