Covington celeron die caps
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H3nrik V!



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PostPosted: Wed Nov 21, 2018 7:39 am    Post subject: Reply with quote

And that little extra question - does the same sspec exist with both small and large die cap?
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CPUShack



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PostPosted: Wed Nov 21, 2018 12:31 pm    Post subject: Reply with quote

Yup, SL2YN is one SL2SY another (and probably a few others)
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H3nrik V!



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PostPosted: Thu Nov 22, 2018 1:46 am    Post subject: Reply with quote

Which question did you answer, John? The one about octagonal die caps or the one about same sspec, different caps? Very Happy
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CPUShack



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PostPosted: Thu Nov 22, 2018 2:38 am    Post subject: Reply with quote

Same sspec diff caps
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H3nrik V!



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PostPosted: Thu Nov 22, 2018 5:03 am    Post subject: Reply with quote

Cool, but how can it be same sspec, if the internals are Covington and Mendocino respectively?

Anyone knows about the octagonal die caps, have they ever been produced/seen in the wild?

http://cdn.cpu-world.com/CPUs/Celeron/S_Intel-BX80523R300000%20(box%20front).jpg
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Chook



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PostPosted: Thu Nov 22, 2018 6:48 am    Post subject: Reply with quote

Yes, but not on Celerons. Early Pentium IIs (Klamath) have the same octagonal die cap. The cache chips of Pentium II Xeon and Pentium II Overdrives also have the octagonal die caps (with two less capacitors than that Celeron box pic.

I suspect that the photo on that box may be an early ES or mech using a PII die (or a PII package at least). Maybe the idea for Celerons came about from Intel having numbers of PII dies with defective L2 cache?

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H3nrik V!



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PostPosted: Thu Nov 22, 2018 10:07 am    Post subject: Reply with quote

Chook wrote:
Yes, but not on Celerons. Early Pentium IIs (Klamath) have the same octagonal die cap. The cache chips of Pentium II Xeon and Pentium II Overdrives also have the octagonal die caps (with two less capacitors than that Celeron box pic.


Yeah, I can see what you mean from the caches. Good point!

Chook wrote:
I suspect that the photo on that box may be an early ES or mech using a PII die (or a PII package at least). Maybe the idea for Celerons came about from Intel having numbers of PII dies with defective L2 cache?

Well, but no Celeron was ever built on 0.35um technology - and what would be the problem with defective L2 - it wasn't on-die anyways ..
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Chook



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PostPosted: Thu Nov 22, 2018 11:28 am    Post subject: Reply with quote

H3nrik V! wrote:
Well, but no Celeron was ever built on 0.35um technology - and what would be the problem with defective L2 - it wasn't on-die anyways ..


Silly me, had forgotten that! You are right. On die cache started with the Mendicino Celerons. Maybe that pic was just a marketing pic made up for the box.

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CPUShack



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PostPosted: Thu Nov 22, 2018 1:02 pm    Post subject: Reply with quote

H3nrik V! wrote:
Cool, but how can it be same sspec, if the internals are Covington and Mendocino respectively?



They are either mendocino dies with the cache disabled, or a Covington die in a mendocino package

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Birdman.



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PostPosted: Thu Nov 22, 2018 3:50 pm    Post subject: Reply with quote

Are there really Covington dies or is it just Deschutes die without external cache?
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H3nrik V!



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PostPosted: Fri Nov 23, 2018 1:23 am    Post subject: Reply with quote

CPUShack wrote:
H3nrik V! wrote:
Cool, but how can it be same sspec, if the internals are Covington and Mendocino respectively?



They are either mendocino dies with the cache disabled, or a Covington die in a mendocino package

If same sspec, shouldn't the internals be the same?
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H3nrik V!



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PostPosted: Fri Nov 23, 2018 2:26 am    Post subject: Reply with quote

Birdman. wrote:
Are there really Covington dies or is it just Deschutes die without external cache?


Yeah, when you asking, I was wondering, how difficult it is to open one to expose the die for you to photograph.

Unfortunately, I only own 2 Covingtons - both small cap - and I think they might begin to be too rare to actually open one?
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