Porbe Mark - Samuel C3 ES

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Neon_WA



Joined: 08 Nov 2008
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Location: Margaret River, West Australia

PostPosted: Wed May 16, 2012 10:59 pm    Post subject: Porbe Mark - Samuel C3 ES Reply with quote

Does anyone know what Porbe Mark means on a 650MHz Samuel core C3 die cap?

Or is it likely a typo for Probe Mark, but that is mainly to do with wire attachment to wafer bonding pads

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Last edited by Neon_WA on Thu May 17, 2012 3:44 am; edited 1 time in total
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Robev



Joined: 10 Mar 2006
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Location: New Zealand

PostPosted: Thu May 17, 2012 12:02 am    Post subject: Re: Porbe Mark - Samuel C3 Reply with quote

Neon_WA wrote:
Does anyone know what Porbe Mark means on a 650MHz Samuel core C3 die cap?

Or is it likely a typo for Probe Mark, but that is mainly to do with wire attachment to wafer bonding pads


I think "porbe" means you be poor if you buy it Laughing Laughing Laughing

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Neon_WA



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PostPosted: Thu May 17, 2012 12:15 am    Post subject: Re: Porbe Mark - Samuel C3 Reply with quote

Robev wrote:
I think "porbe" means you be poor if you buy it Laughing Laughing Laughing

Had to buy a scrap lot to get it... so yes poor at the moment Laughing

cant find any definition for porbe in english or spanish
so guessing is a typo

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Tegranphos



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PostPosted: Thu May 17, 2012 8:41 am    Post subject: Reply with quote

Porbe in spanish don't exist.

"Pobre" is the most similar, and is traduced as poor.

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Neon_WA



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PostPosted: Sun May 20, 2012 7:01 pm    Post subject: Reply with quote

Tegranphos wrote:
Porbe in spanish don't exist.


Good old google translate kept telling me it was Spanish Laughing

Looking at how often the porbe / probe typo is on the web... will follow up and find out more about "Probe Mark" testing

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Neon_WA



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PostPosted: Tue May 22, 2012 7:36 pm    Post subject: Reply with quote

did find this statement in the Samuel datasheet

Certain processors have a proprietary Debug Port which uses the JTAG scan mechanism to control internal
debug features (“probe mode”). These interfaces are not documented and are available (if at all) only
under a non-disclosure agreement.

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Robev



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PostPosted: Tue May 22, 2012 8:15 pm    Post subject: Reply with quote

Neon_WA wrote:
did find this statement in the Samuel datasheet

Certain processors have a proprietary Debug Port which uses the JTAG scan mechanism to control internal
debug features (“probe mode”). These interfaces are not documented and are available (if at all) only
under a non-disclosure agreement.


Better get your Pen ready then Laughing

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Neon_WA



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PostPosted: Tue May 22, 2012 8:36 pm    Post subject: Reply with quote

Robev wrote:
Better get your Pen ready then Laughing

I have dealt with VIA before.. I have 2 chances of getting the info.. zero & none Laughing

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