Instructions Per Cycle for Intel Chips

[Honda00]

Hi All,

I'm by no means a CPU expert. I would like to use this calculator: hpl-calculator.sourceforge.net/

however I don't know what to put in for "Operations per cycle". I believe they are looking for IPC (Instructions per cycle), but I can't find that info for any modern Intel chips.

Does anyone have any wisdom to share?

[Katmai500]

This document might be helpful from two perspectives: 1.) It does provide a lot of data on instruction latencies for difference CPU architectures, 2.) It shows how complex of a thing IPC is to quantify as a single value on a modern CPU.

http://www.agner.org/optimize/instruction_tables.pdf

[Honda00]

Thanks, that clears things up a lot, in as much as there is no exact answer unless addressing a specific chip, and even then it is still a subject for discussion!

[debs3759]

I vaguely remember some of his older documents being useful when I wrote my CPUID code. Haven't worked on that since P4 days though so memories of source material are a little vague

[agent_x007]

Conroe's got ~3,5 IPC.
Haswell can have in theory 5 IPC, but usually it's ~4,2 (?) (if code is "fusion" friendly).
That's of course just guessing in HSW case tho.

Sources :
http://anandtech.com/show/6355/intels-haswell-architecture/6

http://anandtech.com/show/5057/the-bulldozer-aftermath-delving-even-deeper/2

http://www.anandtech.com/show/1998/3