Deschutes TAG ram and cacheable range

[H3nrik V!]

Hi All,

So, if I get it right, some of the Deschutes PII's are using T6P and others T6P-e tagRAM? This should result in different cacheable amount of memory of 512MB or 4GB respectively? Is that correct?

From what I can see with certainty is that the following processors exist with both configurations:

Deschutes 266
Deschutes 333

But what about 300?

And are all 100MHz FSB the T6P-e flavour?

Thanks,

[H3nrik V!]

So, a necro-post seems suitable, since I recently thought about the fact that P2 were available both with 512MiB and 4GiB cacheable range - but does it even make sense, as very few mainboards for P2 supports more than 512 MiB (or 1GiB at most) or am I missing something?

[Katmai500]

This old Tom's Hardware article indicates that all 100 MHz FSB Pentium II's have the T6P-e (82459AD):
https://www.tomshardware.com/reviews/overclocking-special,94-2.html

[H3nrik V!]

Yeah, got most of my knowledge from that article at Tom's

I was actually planning on doing some benchmarks to see what difference it made to use one with 4gb cacheable range vs. one with 512 mb. But it seems not to matter, as most PII chipsets doesn't support more than MAX 1gb - and that needs to be registred SDRAM.