Integration of motorola microprocessors and IPL

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Andy
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PostPosted: Wed Jul 26, 2006 3:42 am    Post subject: Integration of motorola microprocessors and IPL Reply with quote

I am looking to integrate the MC68336/376 and MC68302 microprocessors for a serial communication application. I wish to use the 302 with its CPU disabled as a slave SCP to the 336/376. Is this achievable?

Also i would like to know of the pin allocation on the 336/376 for dealing with IPL (interrupt priority level).
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Andy
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PostPosted: Thu Jul 27, 2006 8:11 am    Post subject: CPU timing and synchronisation Reply with quote

I have answered my own questions above and determined the parts are compatible and sufficiently understand the IPL allocation of the 376. However....

Now it is time to interface the parts and having written the neccessary glue logic to do so, having to implement this into a PLD I am concerned of additional propogation and gate delays which may affect synchronisation.

Also, I am aware that in a similar interface arrangement between the 302 and an EC020, the EC020 produces a half clock timing error which has to be compensated for in the glue logic. Due to the similarities (and differences!) between the 020 and 376 I am unsure if a similar problem will exist with the 376 and 302 arrangement and am having trouble determining the clock differences between the processors.

If anyone can help, or at least give me a little nudge, I would be very grateful.

Andy
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Andy
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PostPosted: Mon Jul 31, 2006 5:38 am    Post subject: Timing advice request Reply with quote

Since these events I have deduced that if using the glue logic from application note AN2021 ("freescale.com/files/netcomm/doc/app_note/AN2021.pdf") implemented in a PLD, the 376 generates the AS, DS, R/W and associated signals ahead of the 302 requirement for them by a margin of between 0.3 and 11.5ns [depending on clock speed, 20.97MHz (max) or 16.67MHz].
Should I add redundant gates at an appropriately lower clock speed to force delay and be on the safe side, or run at full clock speed assuming propagation delay in the tracks and data clocking periods will negate this?

Andy
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