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aberco

Joined: 05 Sep 2013 Posts: 2655 Location: Paris France
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Posted: Sat Nov 16, 2013 6:23 pm Post subject: Mystery chip made by Hitachi on IBM Power4 boards |
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Have you disassembled some Power4 boards, and found this Hitachi chip on it? any idea of what it is?
I think I have a good handle now, but I'll let you propose first and I'll give my answer in several days  |
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CPUShack

Joined: 16 Jun 2003 Posts: 34259 Location: State of Jefferson, USA
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aberco

Joined: 05 Sep 2013 Posts: 2655 Location: Paris France
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Posted: Sat Nov 16, 2013 7:19 pm Post subject: |
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Are you sure? the layout of the PCB does not match, there's no decoupling capacitor or low impedance trace around that chip anywhere. Beside it has a lot of pins for a voltage regulator...
I'd be interested to know the specs of the PA-Risc systems that use these (to confirm my interpretation).
I have an other proposition 
Last edited by aberco on Sat Nov 16, 2013 8:09 pm; edited 1 time in total |
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hugo929

Joined: 27 Oct 2006 Posts: 6163 Location: China
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Posted: Sat Nov 16, 2013 8:07 pm Post subject: |
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Awaiting for your new proposition aberco. Think i also have one but remains mystery. _________________ My vintage CPU collection:www.cpumuseum.com
Chinese Forum: http://www.cpumuseum.com/forum |
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aberco

Joined: 05 Sep 2013 Posts: 2655 Location: Paris France
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Posted: Sat Nov 16, 2013 8:09 pm Post subject: |
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Haha, the proposition I have is nicer than a boring regulator
I will take a good picture tomorrow. |
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CPUShack

Joined: 16 Jun 2003 Posts: 34259 Location: State of Jefferson, USA
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aberco

Joined: 05 Sep 2013 Posts: 2655 Location: Paris France
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Posted: Sat Nov 16, 2013 8:47 pm Post subject: |
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Unlikely. Also the 1.2V is regulated from the outside and is coming from the large busbar connector on the bottom of the board.
The layout of the board does not match what would be required for a voltage regulator, and that's a very fancy package for a regulator as well. You would not use numerous small pads for sourcing a lot of current, even wired in parallel. These are rather I/O signaling pads.
Do you have source? |
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CPUShack

Joined: 16 Jun 2003 Posts: 34259 Location: State of Jefferson, USA
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CPUShack

Joined: 16 Jun 2003 Posts: 34259 Location: State of Jefferson, USA
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aberco

Joined: 05 Sep 2013 Posts: 2655 Location: Paris France
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Posted: Sun Nov 17, 2013 9:50 am Post subject: |
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First surprise, it's a multichip design!
Second surprise, both dies are really large, almost 2x3cm |
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aberco

Joined: 05 Sep 2013 Posts: 2655 Location: Paris France
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Posted: Sun Nov 17, 2013 1:24 pm Post subject: |
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And the die-shot.
Of course only the top metal layer is visible, as this is a modern chip the actual circuitry is not visible. But some parts of the wiring fell off and you can see below the characteristic iridescent pattern of a large memory array.
So my guess is: this is the 32MB L3 cache, split across 2 16MB dies. |
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CPUShack

Joined: 16 Jun 2003 Posts: 34259 Location: State of Jefferson, USA
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Posted: Sun Nov 17, 2013 1:58 pm Post subject: |
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ah ha finally found the right red book, and you are correct:
| Quote: | The L3 merged logic DRAM (MLD) chip, which contains 32 MB of L3 cache.
An eight-way POWER4 SMP module will share 128 MB of L3 cache
consisting of four modules each of which contains two 16 MB merged logic
DRAM chips. |
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aberco

Joined: 05 Sep 2013 Posts: 2655 Location: Paris France
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Posted: Sun Nov 17, 2013 2:42 pm Post subject: |
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I am wondering if next time I can manage to remove just the heatspreader and not rip everything out... the dies and capacitor lifted straight up attached to the heatspreader (after some serious heating on a gas torch).
So that leaves us with the large white IBM ceramic chip on the board... what is it then? a cache controller?
[edit]
Well I will answer myself!
| Quote: | Physically, there are three key components: the POWER4 processor chip, the L3 merged logic DRAM (MLD) chip and the memory controller chip.
- The POWER4 processor chip has two 64-bit microprocessors, a microprocessor interface controller unit, a 1.41-MB L2 cache, an L3 cache directory, a fabric controller responsible for controlling the flow of data and controls on and off the chip, and chip/system pervasive functions.
- The L3 MLD chip contains 16 MB of cache. Two such chips, mounted on their own module, are used for the 32 MB of L3 attached to each POWER4 chip. An 8-way POWER4 SMP module shares 128 MB of L3 cache.
- The memory controller chip features one or two memory data ports and connects to the L3 MLD chips on one side and to the synchronous memory interface (SMI) chips on the other. |
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hugo929

Joined: 27 Oct 2006 Posts: 6163 Location: China
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Posted: Mon Nov 18, 2013 10:25 am Post subject: |
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not bad, multichip cache is nicer than a voltage regulator
btw : is the memory block always red ? _________________ My vintage CPU collection:www.cpumuseum.com
Chinese Forum: http://www.cpumuseum.com/forum |
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aberco

Joined: 05 Sep 2013 Posts: 2655 Location: Paris France
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Posted: Mon Nov 18, 2013 10:39 am Post subject: |
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You mean, the color of the die?
Actually it's a pattern of thin metal wires that makes a diffraction grating, so it's iridescent just like the surface of a CD. It has no color really, other than a copper pink (because of the copper wiring process).
The finer the lithography, and the more iridescent patterns you will see on the die (because the "diffraction grating" will be thinner).
Here only the top wiring can be seen, with a little bit of the actual circuitry peeking below. Most of the memory array should be located on the left and right part of the die, but the metal wiring layer would need to be polished off in order to see it. |
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