is windows wrong about my cpu info?

[varyz]

I currently own an amd a10 5745m and every page says that it counts with 4mb l2 cache, but i can see mine has 8mb and im confused, is it wrong the task manager information?

[Geri]

it says your L1 cache is also doubled than the official specifications. probably windows mistakenly multiples it with two for some reason.

[gshv]

It multiplies by the number of cores, instead of the number of modules (each module contains two cores).

Gennadiy

[xsecret]

Beware of AMD marketing bullshit about what is a "core".

Here is a die shot of your CPU. Knowing that the large area on the right is the GPU. How many real cores do you think you have ?

[Geri]

it isnt marketingbullshit, that is 4 separate core.

the cause of the performance problem of amd cpu-s roots in elsewhere.

the problem is that each amd cpu core have only 4 execution pipeline per core, while intel cpus have 8 pipeline per core.

this means 4 core amd cpus have 4(pipe)*4(core), while intel cpus have 8(pipe)*4(core).

with HT, intel can very efficiently and dynamically partitioning all of its pipelines if there is enough thread in that moment, baiscally all resources of the pipelines are extracted out . if not, so there is not enough threads, the extreme parallerism and performance is guarantied by the existence of the 8 pipeline. (in reality, its limited in most cases like max just 5-6 pipeline per thread usually, and not all 8, but they philosophy matters beyond the design.)

amd cpus are inefficient even with 8 core. the 4(pipe)*8(core) build-up cannot be partitioned. programs with few threads are limited to 4 pipeline per thread in every case, this causing inefficient pipeline usage, both when it have enough pipeline, both if does not

[xsecret]

Can you show me where are the "4 separate core" on that die ?

Your CPU is based on a dual cores deign, each core including 1 front-end, 2 cluster and 1 FPU. That's how AMD engineers named their design and how AMD technical patents describe those parts.

Marketing guys then renamed "cluster" to "cores" and "cores" to "module" because a whooping "8 cores" is much more sexy than a "4 cores with CMT".

[mavroxur]

It smells like behind-the-scenes hyperthreading, not actually 4 cores.

[Geri]

xsecret - sorry, it would took too many time to explain

[xsecret]

Correct I already have spent so many pages to explain this

Edit : Just remember my first paper about BD µarch. I spent hours on Visio to write that schematic :



Unfortunately, all the related text is in French.