[UCA] Xeon ID Shield (Proto)

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xsecret



Joined: 01 Feb 2004
Posts: 1847
Location: France

PostPosted: Tue Jun 05, 2018 1:01 pm    Post subject: [UCA] Xeon ID Shield (Proto) Reply with quote

I'm opening a new thread because the original UCA will soon be used for orders of the UCA & iAPX86 Shield only. New UCA Shield (UCAS) will then be on separated thread.

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Let me introduce another concept for the UCA : the Xeon ID UCAS! I have big plans for the Universal Chip Analyzer as a truly “Universal” chip analyzer, and this is one of them. Xeons are sometimes hard to identify, especially Engineering Sample (ES are often unmarked, available in various flavor with the same part number, or unknown in databases). Xeon motherboard are also a nightmare to work with, expecting exotic RAM, 2- or 4- CPUs, with BIOS restricted to a few S-Spec. Fortunately, “True” Xeon – like MPs but not the rebranded Desktop CPUs – comes with an embedded “PIROM” chip, used by the motherboard to check their specs without booting the whole CPU. The “Xeon ID UCAS” uses that PIROM to ID the unknown Xeon.



The Shield interfaces with Socket probes to connect with the CPU. Right now, I have a working Socket 603/604 Probe and a LGA1567 Probe, but the UCAS should also work with Pentium II/III Xeon (Slot 2) and up to modern Xeon (LGA2011/3467).

Many information can be grabbed that way. Here is an example with a quite-old Xeon (Gallatin) QF75 ES :



And here with a later Xeon (Tulsa) QQBB ES (Intel Xeon 7140M) :



I also made a small video to let you see how it works: https://youtu.be/qbMsxCFOK-I

That’s only a proof-of-concept right now, and the Socket Probe will not be cheap if ever sold, but it looks quite nice

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Universal Chip Analyzer (UCA) : https://x86.fr/uca / http://www.cpu-world.com/forum/viewtopic.php?t=34349
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edwardauskis



Joined: 26 Nov 2014
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PostPosted: Tue Jun 05, 2018 1:05 pm    Post subject: Reply with quote

Shocked Shocked Shocked Shocked Shocked Shocked Shocked
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Vegeta



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PostPosted: Tue Jun 05, 2018 1:11 pm    Post subject: Reply with quote

It's incredible!
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Birdman.



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PostPosted: Tue Jun 05, 2018 4:09 pm    Post subject: Reply with quote

Isn't L3 cache size of that Gallatin incorrect?
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xsecret



Joined: 01 Feb 2004
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Location: France

PostPosted: Tue Jun 05, 2018 4:59 pm    Post subject: Reply with quote

Birdman. wrote:
Isn't L3 cache size of that Gallatin incorrect?


Absolutely! That's a bug in the early firmware: the value is displayed with an unnecessary HEX-to-DEC conversion (16534 = 0x4096 KB). I have added a comment on 0.30 to fix that.

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debs3759



Joined: 18 Jan 2006
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PostPosted: Fri Jun 08, 2018 4:46 pm    Post subject: Reply with quote

I didn't know software could determine QSpec or sSpec.
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xsecret



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PostPosted: Fri Jun 08, 2018 7:25 pm    Post subject: Reply with quote

Yep. And there is a unique serial on each CPU. Seems Intel reintroduced them carefully after the Pentium III scandal in 1999.
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FlashPT



Joined: 01 May 2019
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PostPosted: Wed May 01, 2019 4:22 pm    Post subject: Reply with quote

Very nice.

if you implement like a touch screen you could replace all configuration switches by mcu outputs, do you like the idea?

Thanks

Fernando
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