Intel Pentium III ES - pins removed on purpose? - solved

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Gerwin



Joined: 10 Aug 2012
Posts: 63

PostPosted: Wed Feb 06, 2019 4:00 pm    Post subject: Intel Pentium III ES - pins removed on purpose? - solved Reply with quote

The question at hand is whether this is a CPU damaged by accident - OR - a CPU that has removed pins on purpose, as part of engineering sample testing activities?
Or asked in a different way: has this been seen before on such processors?

SSPEC is QP15ES. It is a coppermine core. The other pins are in good shape. The CPU does not boot at all in a known to be working i440BX system. To my knowledge te removed pins are labelled 'VREF0' and 'Reserved' in the socket 370 specification.

Edit: Deleted attachment because it labelled the pins wrongly, as explained below.


Last edited by Gerwin on Tue Feb 12, 2019 6:27 pm; edited 2 times in total
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CPUShack



Joined: 16 Jun 2003
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PostPosted: Wed Feb 06, 2019 4:42 pm    Post subject: Reply with quote

Those pins were never installed, not missing.

Rather early ES for an 800 so probably had to do with how/what it was testing

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Gerwin



Joined: 10 Aug 2012
Posts: 63

PostPosted: Thu Feb 07, 2019 5:08 pm    Post subject: Reply with quote

Thanks for the quick answer! It will do.

Did you see this on other ES before?
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CPUShack



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PostPosted: Thu Feb 07, 2019 5:29 pm    Post subject: Reply with quote

yup
and I think if you double check the datasheet you will see these are actually

BSEL0 (pin # AJ33)
BSEL1 (pin # AJ31)

This will default the CPU to a 133MHz bus

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Gerwin



Joined: 10 Aug 2012
Posts: 63

PostPosted: Thu Feb 07, 2019 6:34 pm    Post subject: Reply with quote

CPUShack wrote:
yup
and I think if you double check the datasheet you will see these are actually

BSEL0 (pin # AJ33)
BSEL1 (pin # AJ31)

This will default the CPU to a 133MHz bus


BSEL0/BSEL1.. Yeah, that makes much more sense. Like here:
http://www.kilowattalley.com/Marked.jpg


Really not happy with me mixing up pins, but I blame this source:
Upgrading and repairing PCs - 12th edition; it has the same socket 370 pinout as the datasheet and image, but in the book it is labelled "Socket 370 PIII/Celeron pinout (top view)" So that is where things went wrong...
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