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mpe
Joined: 05 Mar 2019 Posts: 10
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Posted: Sun Apr 07, 2019 4:12 pm Post subject: Celeron 300/66 Convington |
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I always thought that cache-less Covington Celeron CPUs have visibly smaller head-spreader than the latter Mendocino.
Now I placed my 300mm SL2X8 (non-A) next to my 266 and that it has much bigger head-spreader. More like the one on 300A/333.
Any idea why is that? Did they ship Mendocino with disabled L2 at some point?
How is everybody's Celeron 300's look like?
On the picture:
top Celeron 266/66 SL2SY
bottom Celeron 300/66 SL2X8 |
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CPUShack

Joined: 16 Jun 2003 Posts: 34259 Location: State of Jefferson, USA
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Posted: Sun Apr 07, 2019 4:47 pm Post subject: |
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Big and small die covers exist for a couple sspecs, I think they stuck the small cacheless dies in the larger package just because it simplified things for production _________________ New for 2025! The CPU Shack has a co-processor!
Visit The CPU Shack of microprocessor history and information. |
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H3nrik V!

Joined: 15 Apr 2014 Posts: 1246 Location: Denmark
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CPUShack

Joined: 16 Jun 2003 Posts: 34259 Location: State of Jefferson, USA
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Posted: Mon Apr 08, 2019 11:30 am Post subject: |
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| H3nrik V! wrote: | http://www.cpu-world.com/forum/viewtopic.php?t=13592&highlight=covington
This is a very interesting thread about that. I think that one theory is that some Covingtons are actually Mendocinos with L2 disabled (maybe faulty) |
yah possible, but one would think CPUID would be able to tell? unless Intel kept the ID the same lol _________________ New for 2025! The CPU Shack has a co-processor!
Visit The CPU Shack of microprocessor history and information. |
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H3nrik V!

Joined: 15 Apr 2014 Posts: 1246 Location: Denmark
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Posted: Tue Apr 09, 2019 3:11 am Post subject: |
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| CPUShack wrote: | | H3nrik V! wrote: | http://www.cpu-world.com/forum/viewtopic.php?t=13592&highlight=covington
This is a very interesting thread about that. I think that one theory is that some Covingtons are actually Mendocinos with L2 disabled (maybe faulty) |
yah possible, but one would think CPUID would be able to tell? unless Intel kept the ID the same lol |
Agreed, I believe that what you write about just using large cover for simplification of production is more plausible. |
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mpe
Joined: 05 Mar 2019 Posts: 10
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Posted: Tue Apr 09, 2019 4:04 am Post subject: |
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It would be interesting to de-lid one of these 300 MHz Celerons and compare to see if the cache is there or not.
Is that feasible? |
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H3nrik V!

Joined: 15 Apr 2014 Posts: 1246 Location: Denmark
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Posted: Tue Apr 09, 2019 5:42 am Post subject: |
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| mpe wrote: | It would be interesting to de-lid one of these 300 MHz Celerons and compare to see if the cache is there or not.
Is that feasible? |
Probably - but that calls for someone being willing to sacrifice a chip for the cause (actually probably two - one big, one small) .. |
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