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H3nrik V!
Joined: 15 Apr 2014
Posts: 1246
Location: Denmark
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 Posted: Tue Jun 25, 2019 1:28 am Post subject: Pentium Classic vs. MMX difference? |
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According to page 1 of this article https://www.anandtech.com/show/53 a difference between P54C and P55 was
| Quote: | | Taking after the Pentium Pro, the Pentium MMX has a highly advanced core, much more advanced than the Classic Pentium. It is because of this that a Pentium MMX-166 can outperform its 200MHz Classic brother. |
Is this actually the case, or an early misunderstanding?
The performance gap shown here https://www.vogons.org/viewtopic.php?f=46&t=34666 could in my opinion easily be explained by the double L1 cache. What are your thoughts on this? |
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rjluna2
Joined: 27 Oct 2014
Posts: 1302
Location: Hiram, GA, USA
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mpe
Joined: 05 Mar 2019
Posts: 10
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| Posted: Tue Jun 25, 2019 11:33 am Post subject: |
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There were actually more changes. Such as improved branch predictor, extra pipeline stage, more istructions can be scheduled in parallel, etc.. Also the L1 cache association is now 4way vs 2way.
All these give MMX a really nice boost. |
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debs3759
Joined: 18 Jan 2006
Posts: 9477
Location: Northampton, Divided Kingdom
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| Posted: Tue Jun 25, 2019 11:36 am Post subject: |
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| mpe wrote: | There were actually more changes. Such as improved branch predictor, extra pipeline stage, more istructions can be scheduled in parallel, etc.. Also the L1 cache association is now 4way vs 2way.
All these give MMX a really nice boost. |
Only in apps specifically written to use the new features, evidently 
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H3nrik V!
Joined: 15 Apr 2014
Posts: 1246
Location: Denmark
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| Posted: Wed Jun 26, 2019 12:27 am Post subject: |
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| mpe wrote: | There were actually more changes. Such as improved branch predictor, extra pipeline stage, more istructions can be scheduled in parallel, etc.. Also the L1 cache association is now 4way vs 2way.
All these give MMX a really nice boost. |
Well the extra pipeline stage, could on the other hand actually negatively affect the IPC
Edit: Hopefully the improved branch prediction should minimize this impact, though .. |
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mpe
Joined: 05 Mar 2019
Posts: 10
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| Posted: Tue Jul 02, 2019 5:35 pm Post subject: |
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according to Intel white-paper. The IPC cost of the extra pipeline stage was about 5-6%. However, it:
- enabled 233 MHz model
- was more than compensated by branch predictor improvements (+8%), cache doubling/reorg. (+7% to +10%) and bus tweaks (+5%).
So overall MMX performance gain is about 15% clock to clock. That's without using any MMX. |
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cuttingedgecs
Joined: 08 Oct 2017
Posts: 1764
Location: Australia
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| Posted: Tue Jul 02, 2019 7:03 pm Post subject: |
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| mpe wrote: |
So overall MMX performance gain is about 15% clock to clock. That's without using any MMX. |
From what I remember, that 15% figure was is best case scenario (ie on all of the Intel marketing materials). Some business applications benefited that much from the cache and improved branch prediction, but for games, compression and non-MMX enhanced multimedia programs there was little to no difference. Still, I never saw anything that ran slower on an MMX. It would have to be a workload with a lot of mispredicts. |
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mpe
Joined: 05 Mar 2019
Posts: 10
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| Posted: Wed Jul 03, 2019 2:47 am Post subject: |
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Yes. It all depends on the software. If you run a software that is not heavy on branching, such as this amazing branchless mov-only Doom port:
https://github.com/xoreaxeaxeax/movfuscator/tree/master/validation/doom
Then you are less likely to benefit from branch predictor improvements
Similarly if all you code fits in 8K the bigger cache can't help.
But normal software should be fine and there should be healthy gains.
I would be so happy if Intel achieved similar performance gains between modern CPUs generations |
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