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Vladislav0504
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 Posted: Tue Dec 03, 2019 1:27 pm Post subject: TLB/Cache details of the modern processors |
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| Hello! I would like to know answer on the following question. Why do Intel processors without Hyper Threading technology have twice the number of entries for Instruction TLB than processors with this technology? For example, Instruction TLB: 4-KByte pages, 8-way set associative, 128 entries - i7-9700k and Instruction TLB: 4-KByte pages, 8-way set associative, 64 entries - i9-9900k. |
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