POWER6
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ghost
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PostPosted: Wed Oct 25, 2006 6:29 pm    Post subject: POWER6 Reply with quote

Does anyone have any information about the upcoming POWER6 family?
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CPUShack



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PostPosted: Thu Oct 26, 2006 12:23 am    Post subject: Reply with quote

yes it is a bloody impressive chip
0.8V 65nm and 5GHz

http://www.eetimes.com/news/design/showArticle.jhtml;jsessionid=4IKU2SBEOKQIYQSNDLPSKHSCJUNN2JVN?articleID=193105767

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slava



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PostPosted: Sat Oct 28, 2006 12:36 am    Post subject: Reply with quote

LOL
... and Apple now uses Pentiums Smile

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PostPosted: Sat Oct 28, 2006 3:29 am    Post subject: Reply with quote

Yep apple suck.

I dont know why you'd move away from a full RISC based machine to CISC?? Do they want market share that badly???

I've deployed a few of the Mac Pro's at work, there not bad.... but they still under perform the PPC versions which are almost 3 years old.

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CPUShack



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PostPosted: Sat Oct 28, 2006 11:46 pm    Post subject: Reply with quote

Core2duo is full RISC (as is P3 and P4)
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Marcin



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PostPosted: Sun Oct 29, 2006 2:27 am    Post subject: Reply with quote

AMD Athlon 64 is RISC too. AMD is RISC from K5 to present day. Am I right ?
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PostPosted: Sun Oct 29, 2006 9:38 am    Post subject: Reply with quote

Ah no, Intel processors use a hybrid CISC/RISC architecture. Interally they process RISC base instructions but a CISC/RISC decoder is used to convert the frontside operation which only accpets CISC instructions.

This is done for compatibility with the x86 architecture. Something which AMD also does.
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chip68



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PostPosted: Sun Oct 29, 2006 10:24 am    Post subject: Reply with quote

Anonymous wrote:
Do they want market share that badly???


This is Steve Jobs we're talking about... So, YES.

- CMW
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CPUShack



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PostPosted: Sun Oct 29, 2006 3:37 pm    Post subject: Reply with quote

Anonymous wrote:
Ah no, Intel processors use a hybrid CISC/RISC architecture. Interally they process RISC base instructions but a CISC/RISC decoder is used to convert the frontside operation which only accpets CISC instructions.

This is done for compatibility with the x86 architecture. Something which AMD also does.


yup, but the CPU remains a RISC architecture regardless.

the translation (into a series of RISC uOPs ) is rather seemless, and actually hels speed up execution of alot of things, as the decoder can decode things in a way to best use the available pipelines (each CISC instruction can be broken down into several different (but same output wise) uOPs series.)

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Root



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PostPosted: Sun Oct 29, 2006 5:31 pm    Post subject: Reply with quote

Quote:
yup, but the CPU remains a RISC architecture regardless.

We must examine CPU in all aspects. In this point of view, modern x86 CPUs aren't pure RISC, but CISC with RISC-core.
Quote:
each CISC instruction can be broken down into several different (but same output wise) uOPs series.)

There is only one reason for holding CISC instruction set - compatibility with older software. Perfomance will be better if CPU will be pure RISC with good written programs.
So I agree with Guest

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CPUShack



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PostPosted: Sun Oct 29, 2006 7:08 pm    Post subject: Reply with quote

sure, but POWER6 is by far not pure RISC either (very few modern RISC CPU's truly are. they have a very large selection of instructions, and often do not have basic features that make RISC RISC (such as fixed instruction length, and pure load/store architecture.)
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PostPosted: Mon Oct 30, 2006 3:17 am    Post subject: Reply with quote

Why don't 'YOU' consider it RISC?
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Root



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PostPosted: Tue Oct 31, 2006 8:21 pm    Post subject: Reply with quote

As I remember newest PowerPC has
a) instruction with fixed length
b) a lot of registers in opposite to classical x86.
...
z) IBM said that PowePC is RISC. I think that they have reasons for it.
So we can consider it as RISC Smile

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CPUShack



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PostPosted: Tue Oct 31, 2006 10:30 pm    Post subject: Reply with quote

hehe never said it wasnt RISC, just that it isnt RISC in true from, (though what is today? except for perhaps MIPS)
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PostPosted: Fri Nov 03, 2006 5:11 am    Post subject: Reply with quote

But it is a truth RISC based procesors, I mean unless you know more about RISC then IBM does...

has something to do with POWER (Performance Optimization With Enhanced RISC)???

Smile
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