HP identification

[Tonyo]

can U help me to identificate this cpu

thx

[unte13]

Believed to be a HP 5960-1342 revB 100 mhz CPU.
really nice chip.
Congratulations.

[doccybrown]

...also known as PA-7100LC!
/Doccy

[unte13]

Well exact.
I like its name: Hummingbird!
PA-7100LC (PCX-L) (Hummingbird)
Used in

* 712/{60,80,100}
* 715/{64,80,100}
* 725/100
* 743i/{64,100}
* 748i/{64,100}
* D200, D210, D300, D310
* E25, E35, E45, E55
* Hitachi 3050RX 225, 235
* SAIC Galaxy 1100

Time of introduction

1994
Overview

The PA-7100LC was primarily designed as a single-chip solution for application in low cost systems while still delivering the performance of '91 high-end workstations and servers. Contrary to earlier PA-RISC version 1.1 implementations which needed several support chips for the MPU the PA-7100LC integrates the CPU, FPU, MIOC (memory and I/O controller) and a first-level cache on a single VLSI chip. Both CPU and FPU support the PA-RISC 1.1 Edition 3 ISA.
Details

* PA-RISC version 1.1c 32-bit
* 3 functional units: 2 integer ALUs, 1 Floating Point unit1
* 2-way superscalar
* DRAM-memory & cache controller (MIOC) integrated on die
* 1KB on-chip I L1 instruction cache, direct mapped, 64-bit per access, prefetch from off-chip I cache
* 8KB-2MB off-chip unified I/D L1 cache, direct mapped, hashed address, virtual index, 480-600MB/s bandwidth
* (the 1KB on-chip I cache is not really considered a true cache, thus the off-chip cache in fact is the system's real L1 cache.)
* 32-Byte cache line size
* support for bi-endian load-store operations
* MAX-1 multimedia extensions (subword arithmetic) for multimedia applications, e.g. MPEG decoding
* Floating Point load-store to I/O space
* 64-entry unified I/D TLB, fully associative, 4K page size
* 8-entry BTLB, page sizes from 512K - 64M
* 64-bit wide load/store operations
* I and D cache bypassing
* stall on use D cache miss policy
* don't fill on miss cache hint
* hardware TLB miss handler support
* hardware static branch prediction
* GSC bus interface
* 64-bit ECC interface to the main memory
* instruction line prefetch from main memory
* up to 100MHz clock
* not MP capable
* 14.2 x 14.2 mm2 die, 900'000 FETs, 0.75 micron, 3-layer aluminium process packaged in a 432-pin PGA

1. Only one of the two integer ALUs is able to handle loads, stores and shifts, these operations can only be paired with simple math operations, like integer addition or multiplication. Both units can handle branch operations.

[Tonyo]

great !!

Thx

[Sten]

Hi unte13
How could you know that this chip is 100Mhz version?
I have the same one, but without MB.
Please advise
Thanks
Best Rgrds
Sten

[unte13]

PA7100LC is recognizable with (1FT2-xxxx)
so PA7100 is 100 MHz.
You find relevant information here:

http://www.openpa.net
Have you got a picture?

[Sten]

Whow Iam really impressed.
Great thanks for info
Here is the pic.

[unte13]

Really nice chip.
But for the nec chips, I have no idea at all.