Balance 90nm

[Tekken]

Hi,

These are perhaps weird questions, but I really need answers. Speculation is also welcome.


How fast is the avarage speed of the transistors used in any particular 90nm CPU?

What is the dimensions of an avarage 'blob' of doped chrystal silicon(or whatever is used) in the above 90nm process?

What is the avarage 'safe' space between the 90nm wires?

What is the avarage 'safe' space between the chrystals/transistors?

How many wiring layers can be applied to a waffer used for the above?

What is the avarage speed percentage of "c",'through' the wires for signal/impulse?

What is the avarage speed percentage of "c",'through' the chrystals for signal/impulse, after the chrystal has settled?


Avarage data would be great. Precision, ratio/chance, and highs/lows would be perfect. As much data or links to this as possible, please. Relevant unit for answers should be trivial.

Thanks all, hope you can answer or get me closer any to the anwsers.

[skold]

i cant speak for anyone else, but i think your questions are far too technical for this forum... i dont think anyone here is an engineer?