missing pin in Celeron 1000A SL5VP

[Tegranphos]

Hello, I recently found 2 Celeron 1000A SL5VP but the two chips have the same pin missing (first in one corner) and my question is: Is it normal or I have bad lucky?

Sorry but no photo, my camera said good bye when i try take the photo :_(

[mavroxur]

Socket 370 has one "missing" pin in two corners. Is this what you're talking about?

[Tegranphos]

mmm... ovbiously... not.

Te CPU with the two corners with the oficialy missing pins in down, and in the left inferior corner, first pin and two more that not seeing after.

[Tegranphos]

Photo-shop with red marked missing pins in the two procesors.

[Tegranphos]

OK, mistery solved, inclompleted mod, the overclocker not make the jumper xD:

http://www.oocities.org/_lunchbox/ms6905_tualatin_mod.html

http://www.overclockers.com/forums/showthread.php?t=67417&pp=50&page=5

http://www.overclockers.com/forums/archive/index.php/t-73195.html

[Neon_WA]

what i was thinking seeing what the pins were for

from left to right
Pin A3 > AGTL I/O
Pin E3 > AGTL I/O
Pin D4 > AGTL I/O

[Tegranphos]

wow sorry, two days without sleep and anybody will forgot that pins are inverted xD

New photo: when i put the chip in it, the red pins are the pins that are missing. I hope that this time is OK xD

[Neon_WA]

pins from top to bottom

AN3 > DYN_OE
AK4 > VttPWRGD
AJ3 > RESET2#

The DYN_OE allows the BSEL and VID signals to be driven out from the processor.
When this signal is low (a condition that will occur if the Intel® Pentium® III
processor is installed in a non-supported platform), the VID and BSEL signals will
be tri-stated and the platform pull-up resistors will set the VID and BSEL to all ‘1’s’
which is a safe setting.

The VTT_PWRGD signal informs the system that the VID/BSEL signals are in their
correct logic state. During Power-up, the VID signals will be in a indeterminate state
for a small period of time. The voltage regulator or the VRM should not sample and/
or latch the VID signals until the VTT_PWRGD signal is asserted. The assertion of
the VTT_PWRGD signal indicates the VID signals are stable and are driven to the
final state by the processor.

RESET2# pin is provided to differentiate the Intel® Pentium® III processor with
512KB L2 Cache from legacy Pentium® III processors. The Intel® Pentium® III
processor with 512KB L2 Cache. does not use the RESET2# pin.